1. Field of the Invention
The present invention relates to a semiconductor device comprising a circuit pattern group including metal wire, gate, diffusion, dummy and so on, a method for making a pattern layout of a plurality of circuit patterns in a circuit pattern group, further a method for making a mask pattern based on design data of a semiconductor device, a method for manufacturing a photo mask by using the method for making a mask pattern; a photo mask; a method for manufacturing a semiconductor device using the photo mask, and a method for making a layout to correct design data.
2. Description of the Related Art
Recently, technologies for manufacturing a semiconductor have been remarkably developed. Currently, a semiconductor device with a minimum processing dimension of 90 nm has been mass-produced. Miniaturization of the semiconductor device is realized by rapid development in the fine pattern forming technology. As a typical fine pattern forming technology, a mask process technology, a lithography process technology, and an etching process technology may be referred.
In an age that a pattern size is very large, a mask comprising a mask pattern which is the same shape as that of a design pattern is made, the mask is set in an aligner, and a pattern is comparatively easily formed on a wafer as designed by transferring the mask pattern onto a resist applied on the wafer.
However, it is difficult to form a pattern on a wafer as designed because a pattern size becomes smaller at present. The reason is that diffraction of exposure light has a large influence on the dimension of a pattern on a wafer, it is difficult to manufacture a mask for forming a fine pattern and a fine pattern on a wafer is difficult with high accuracy.
Correction methods such as called optical proximity correction (OPC), and process proximity correction (PPC) (Jpn. Pat. Appln. KOKAI Publication Nos. 2001-13668, and 2003-17390) is known as a technology to improve the fidelity of a design pattern.
The correction method such as OPC and PPC (hereinafter, both of OPC and PPC will be expressed as PPC) is roughly classified into rule based PPC, and model-based PPC.
The rule based PPC is a method by which a moving amount of an edge forming the design pattern is defined as a rule (table) according to the width of a design pattern, the nearest distance between patterns, and the like, and the optimal moving amount (correction amount) of the edge is acquired according to the rule (table).
On the other hand, in the model-based PPC, the optimal moving amount (correction amount) of the edge is acquired in such a way that the same pattern as a design pattern is formed on a wafer by using a lithography simulator by which the diffracted light intensity distribution of the exposure light can be estimated with high accuracy.
There has been also proposed another correction method for realizing higher accuracy by combining the rule based PPC and the model-based PPC.
Recently, not only PPC (a technology correcting a mask pattern), but also a technology modifying design pattern for improving the process margin, called target mask data processing (MDP) is also proposed.
In the target MDP processing, a specific kind of a pattern which is estimated difficult to be formed on a wafer is corrected in such a way that the specific kind of pattern is easily formed on the wafer.
In the target MDP processing, a final design pattern is changed to a pattern different from an original one made by a designer. Thereby, it is required to promote the target MDP processing after gaining the consent of the designer beforehand on how to change the pattern. Accordingly, operation of the target MDP processing is complex.
It has been difficult in recent years to secure a process margin in lithography process. Thereby, a technology by which the shape of a design pattern is changed in a more complex manner is required for the target MDP processing. However, it is difficult to establish such a technology for changing the pattern.
Incidentally, a NAND type flash memory has been known as one of nonvolatile semiconductor storage device. The NAND type flash memory comprises a memory cell array connecting a plurality of memory cells in series. The memory cell comprises a MOS structure in which a floating gate and a control gate are accumulated. The NAND type flash memory has a merit that it is suitable for high integration.
However, as mentioned above, the development of the lithography process is not good enough to the miniaturization of the semiconductor device, it has been in a situation that higher integration of the NAND type flash memory is difficult. Specifically, the higher integration can not be realized when a conventional circuit pattern layout for the NAND type flash memory (Jpn. Pat. Appln. KOKAI Publication No. 2002-64043) is reduced as it is.